IN3	1  •	28	IN2
IN4	2	27	IN1
IN5	3	26	IN0
IN6	4	25	A0
IN7	5	24	A1
START	6	23	A2
EOC	7	22	ALE
D3	8	21	D7
OUTPUT ENABLE	9	20	D6
CLOCK	10	19	D5
VCC	11	18	D4
VREF (+)	12	17	D0
GND	13	16	VREF (-)
D1	14	15	D2

Pin	Symbol	Description
1	IN3	analog input 3
2	IN4	analog input 4
3	IN5	analog input 5
4	IN6	analog input 6
5	IN7	analog input 7
6	START	start conversion (active high)
7	EOC	end of conversion (active high)
8	D3	data bus
9	OUTPUT ENABLE	data output enable
10	CLOCK	clock input
11	VCC	supply voltage
12	VREF (+)	positive voltage reference
13	GND	ground
14	D1	data bus
15	D2	data bus
16	VREF (-)	negative voltage reference
17	D0	data bus (LSB)
18	D4	data bus
19	D5	data bus
20	D6	data bus
21	D7	data bus (MSB)
22	ALE	address latch enable (positive-edge trigger)
23	A2	channel select (MSB)
24	A1	channel select
25	A0	channel select (LSB)
26	IN0	analog channel 0
27	IN1	analog channel 1
28	IN2	analog channel 2

Specifications
(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Supply voltage VCC	5	V
Total unadjusted error	±1/2 (ADC0808) ±1 (ADC0809)	LSB
Input resistance, VREF (+) to VREF (-)	2.5	k Ω
Analog input voltage range	GND-0.10 (min) Vcc+0.10 (max)	V
Minimum START pulse width	100	ns
Minimum ALE pulse width	100	ns
Analog mux delay time from ALE	1	µs
Conversion time (640 kHz clock frequency)	100	µs
Clock frequency	10 (min) 640 (typical) 1280 (max)	kHz