Circuitos Integrados

74646
Octal bus transceiver/register; 3-state
PDF datasheet
       
CPAB 1  • 24 Vcc
SAB 2 23 CPBA
DIR 3 22 SBA
A0 4 21 OE
A1 5 20 B0
A2 6 19 B1
A3 7 18 B2
A4 8 17 B3
A5 9 16 B4
A6 10 15 B5
A7 11 14 B6
GND 12 13 B7
       
Pin Symbol Description
1 CPAB A to B clock input (low-to-high, edge-triggered)
2 SAB select A to B source input
3 DIR direction control input
4 A0 A data input/output
5 A1 A data input/output
6 A2 A data input/output
7 A3 A data input/output
8 A4 A data input/output
9 A5 A data input/output
10 A6 A data input/output
11 A7 A data input/output
12 GND ground
13 B7 B data input/output
14 B6 B data input/output
15 B5 B data input/output
16 B4 B data input/output
17 B3 B data input/output
18 B2 B data input/output
19 B1 B data input/output
20 B0 B data input/output
21 OE output enable (active low)
22 SBA select B to A source input
23 CPBA B to A clock input (low-to-high, edge-triggered)
24 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, An , Bn to Bn , An 11 (74HC)
13 (74HCT)
ns
Maximum clock frequency 69 (74HC)
85 (74HCT)
MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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