Circuitos Integrados

74597
8-bit shift register with input flip-flops
PDF datasheet
       
D1 1  • 16 Vcc
D2 2 15 D0
D3 3 14 DS
D4 4 13 PL
D5 5 12 STCP
D6 6 11 SHCP
D7 7 10 MR
GND 8 9 Q
       
Pin Symbol Description
1 D1 parallel data input
2 D2 parallel data input
3 D3 parallel data input
4 D4 parallel data input
5 D5 parallel data input
6 D6 parallel data input
7 D7 parallel data input
8 GND ground
9 Q serial data output
10 MR asynchronous master reset (active low)
11 SHCP shift clock input (low-to-high, edge-triggered)
12 STCP storage clock input (low-to-high, edge-triggered)
13 PL parallel load input (active low)
14 DS serial data input
15 D0 parallel data input
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, SHCP to Q 17 (74HC)
20 (74HCT) 		ns
Propagation delay, STCP to Q 25 (74HC)
29 (74HCT) 		ns
Propagation delay, PL to Q 21 (74HC)
26 (74HCT) 		ns
Maximum clock frequency, SHCP 96 (74HC)
83 (74HCT) 		MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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