1CP 0	1  •	16	Vcc
1MR	2	15	2CP 0
1Q0	3	14	2MR
1CP 1	4	13	2Q0
1Q1	5	12	2CP 1
1Q2	6	11	2Q1
1Q3	7	10	2Q2
GND	8	9	2Q3

Pin	Symbol	Description
1	1CP 0	clock input, divide-by-2 section (high-to-low, edge-triggered)
2	1MR	asynchronous master reset (active high)
3	1Q0	flip-flop output
4	1CP 1	clock input, divide-by-5 section (high-to-low, edge-triggered)
5	1Q1	flip-flop output
6	1Q2	flip-flop output
7	1Q3	flip-flop output
8	GND	ground
9	2Q3	flip-flop output
10	2Q2	flip-flop output
11	2Q1	flip-flop output
12	2CP 1	clock input, divide-by-5 section (high-to-low, edge-triggered)
13	2Q0	flip-flop output
14	2MR	asynchronous master reset (active high)
15	2CP 0	clock input, divide-by-2 section (high-to-low, edge-triggered)
16	Vcc	supply voltage

Specifications
(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, nCP 0 to nQ0	14 (74HC) 18 (74HCT)	ns
Propagation delay, nCP 1 to nQ1	15 (74HC) 19 (74HCT)	ns
Propagation delay, nCP 1 to nQ2	23 (74HC) 26 (74HCT)	ns
Propagation delay, nCP 1 to nQ3	15 (74HC) 19 (74HCT)	ns
Propagation delay, nMR to nQn	16 (74HC) 18 (74HCT)	ns
Maximum clock frequency, nCP 0 and nCP 1	66 (74HC) 61 (74HCT)	MHz