| Circuitos Integrados | ||
|---|---|---|
| 74259 |
|---|
| 8-bit addressable latch |
| PDF datasheet |
| A0 | 1 • | 16 | Vcc |
| A1 | 2 | 15 | MR |
| A2 | 3 | 14 | LE |
| Q0 | 4 | 13 | D |
| Q1 | 5 | 12 | Q7 |
| Q2 | 6 | 11 | Q6 |
| Q3 | 7 | 10 | Q5 |
| GND | 8 | 9 | Q4 |
| Pin | Symbol | Description |
|---|---|---|
| 1 | A0 | address input |
| 2 | A1 | address input |
| 3 | A2 | address input |
| 4 | Q0 | latch output |
| 5 | Q1 | latch output |
| 6 | Q2 | latch output |
| 7 | Q3 | latch output |
| 8 | GND | ground |
| 9 | Q4 | latch output |
| 10 | Q5 | latch output |
| 11 | Q6 | latch output |
| 12 | Q7 | latch output |
| 13 | D | data input |
| 14 | LE | latch enable input (active low) |
| 15 | MR | conditional reset input (active low) |
| 16 | Vcc | supply voltage |
| Specifications |
|---|
| (typical values under recommended operating conditions, unless specified) |
| Parameter | Value | Unit |
|---|---|---|
| Propagation delay, D to Qn |
18 (74HC) 20 (74HCT) |
ns |
| Propagation delay, An to Qn |
17 (74HC) 20 (74HCT) |
ns |
| Propagation delay, LE to Qn |
17 (74HC) 20 (74HCT) |
ns |
| Note |
|---|
| Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information. |
| BACK |