Circuitos Integrados

74237
3-to-8 line decoder/demultiplexer with address latches; non-inverting
PDF datasheet
       
A0 1  • 16 Vcc
A1 2 15 Y0
A2 3 14 Y1
LE 4 13 Y2
E 1 5 12 Y3
E2 6 11 Y4
Y7 7 10 Y5
GND 8 9 Y6
       
Pin Symbol Description
1 A0 data input 0
2 A1 data input 1
3 A2 data input 2
4 LE latch enable input (active low)
5 E 1 data enable input 1 (active low)
6 E2 data enable input 2 (active high)
7 Y7 output 7
8 GND ground
9 Y6 output 6
10 Y5 output 5
11 Y4 output 4
12 Y3 output 3
13 Y2 output 2
14 Y1 output 1
15 Y0 output 0
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, An to Yn 16 (74HC) ns
Propagation delay, LE to Yn 19 (74HC) ns
Propagation delay, E 1 to Yn 14 (74HC) ns
Propagation delay, E2 to Yn 14 (74HC) ns

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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