MR	1  •	16	VCC
J	2	15	Q0
K	3	14	Q1
P0	4	13	Q2
P1	5	12	Q3
P2	6	11	Q 3
P3	7	10	CP
GND	8	9	PE

Pin	Symbol	Description
1	MR	Asynchronous Master Reset (Active Low)
2	J	First Stage J Input (Active High)
3	K	First Stage K Input (Active Low)
4	P0	Parallel Data Input
5	P1	Parallel Data Input
6	P2	Parallel Data Input
7	P3	Parallel Data Input
8	GND	Ground
9	PE	Parallel Enable Input (Active Low)
10	CP	Clock Pulse Input (Active Rising Edge)
11	Q 3	Complementary Last Stage Output (Active Low)
12	Q3	Parallel Outputs
13	Q2	Parallel Outputs
14	Q1	Parallel Outputs
15	Q0	Parallel Outputs
16	VCC	Power