| Circuitos Integrados | ||
|---|---|---|
| 74193 |
|---|
| Presettable synchronous 4-bit binary up/down counter; separate up/down clocks |
| PDF datasheet |
| D1 | 1 • | 16 | Vcc |
| Q1 | 2 | 15 | D0 |
| Q0 | 3 | 14 | MR |
| CPD | 4 | 13 | TCD |
| CPU | 5 | 12 | TCU |
| Q2 | 6 | 11 | PL |
| Q3 | 7 | 10 | D2 |
| GND | 8 | 9 | D3 |
| Pin | Symbol | Description |
|---|---|---|
| 1 | D1 | data input |
| 2 | Q1 | counter output |
| 3 | Q0 | counter output |
| 4 | CPD | count down clock input (low-to-high, edge-triggered) |
| 5 | CPU | count up clock input (low-to-high, edge-triggered) |
| 6 | Q2 | counter output |
| 7 | Q3 | counter output |
| 8 | GND | ground |
| 9 | D3 | data input |
| 10 | D2 | data input |
| 11 | PL | parallel load input (active low) |
| 12 | TCU | terminal count up (carry) output (active low) |
| 13 | TCD | terminal count down (borrow) output (active low) |
| 14 | MR | asynchronous master reset (active high) |
| 15 | D0 | data input |
| 16 | Vcc | supply voltage |
| Specifications |
|---|
| (typical values under recommended operating conditions, unless specified) |
| Parameter | Value | Unit |
|---|---|---|
| Propagation delay, CPU, CPD to Qn |
23 (74HC) 23 (74HCT) |
ns |
| Propagation delay, CPU to TCU , TCD |
14 (74HC) 15 (74HCT) |
ns |
| Propagation delay, PL to Qn |
25 (74HC) 26 (74HCT) |
ns |
| Propagation delay, MR to Qn |
21 (74HC) 22 (74HCT) |
ns |
| Propagation delay, Dn to Qn |
25 (74HC) 27 (74HCT) |
ns |
| Propagation delay, PL to TCU , TCD |
29 (74HC) 31 (74HCT) |
ns |
| Propagation delay, MR to TCU , TCD |
27 (74HC) 29 (74HCT) |
ns |
| Propagation delay, CPU, Dn to TCU , TCD |
29 (74HC) 32 (74HCT) |
ns |
| Maximum frequency |
41 (74HC) 43 (74HCT) |
MHz |
| Note |
|---|
| Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information. |
| BACK |