Circuitos Integrados

74166
8-bit parallel-in/serial-out shift register
PDF datasheet
       
Ds 1  • 16 Vcc
D0 2 15 PE
D1 3 14 D7
D2 4 13 Q7
D3 5 12 D6
CE 6 11 D5
CP 7 10 D4
GND 8 9 MR
       
Pin Symbol Description
1 Ds serial data input
2 D0 parallel data input
3 D1 parallel data input
4 D2 parallel data input
5 D3 parallel data input
6 CE clock enable input (active low)
7 CP clock input (low-to-high, edge-triggered)
8 GND ground
9 MR asynchronous master reset (active low)
10 D4 parallel data input
11 D5 parallel data input
12 D6 parallel data input
13 Q7 serial output from the last stage
14 D7 parallel data input
15 PE parallel enable input (active low)
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, CP to Q7 15 (74HC)
20 (74HCT) 		ns
Propagation delay, MR to Q7 14 (74HC)
19 (74HCT) 		ns
Maximum clock frequency 63 (74HC)
50 (74HCT) 		MHz

Notes
  • The low-to-high transition of CE should only take place while CP is high for predictable operation.
  • A low on MR overrides all other inputs and clears the register asynchronously, forcing all bit positions to a low stage.

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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