MR	1  •	16	Vcc
CP	2	15	TC
D0	3	14	Q0
D1	4	13	Q1
D2	5	12	Q2
D3	6	11	Q3
CEP	7	10	CET
GND	8	9	PE

Pin	Symbol	Description
1	MR	synchronous master reset (active low)
2	CP	clock input (low-to-high, edge-triggered)
3	D0	data input
4	D1	data input
5	D2	data input
6	D3	data input
7	CEP	count enable input
8	GND	ground
9	PE	parallel load enable input (active low)
10	CET	count enable carry output
11	Q3	counter output
12	Q2	counter output
13	Q1	counter output
14	Q0	counter output
15	TC	terminal count output
16	Vcc	supply voltage

Specifications
(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Propagation delay, CP to Qn	17 (74HC) 20 (74HCT)	ns
Propagation delay, CP to TC	21 (74HC) 25 (74HCT)	ns
Propagation delay, CET to TC	11 (74HC) 14 (74HCT)	ns
Maximum clock frequency	51 (74HC) 50 (74HCT)	MHz