Circuitos Integrados

74137
3-to-8 line decoder/demultiplexer with address latches; inverting
PDF datasheet
       
A0 1  • 16 Vcc
A1 2 15 Y 0
A2 3 14 Y 1
LE 4 13 Y 2
E 1 5 12 Y 3
E2 6 11 Y 4
Y 7 7 10 Y 5
GND 8 9 Y 6
       
Pin Symbol Description
1 A0 data input 0
2 A1 data input 1
3 A2 data input 2
4 LE latch enable input (active low)
5 E 1 data enable input 1 (active low)
6 E2 data enable input 2 (active high)
7 Y 7 output 7
8 GND ground
9 Y 6 output 6
10 Y 5 output 5
11 Y 4 output 4
12 Y 3 output 3
13 Y 2 output 2
14 Y 1 output 1
15 Y 0 output 0
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, An to Y n 18 (74HC) ns
Propagation delay, LE to Y n 17 (74HC) ns
Propagation delay, E 1 to Y n 15 (74HC) ns
Propagation delay, E2 to Y n 15 (74HC) ns

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

BACK