Circuitos Integrados

74109
Dual J-K flip-flop with set and reset; positive-edge trigger
PDF datasheet
       
1R D 1  • 16 Vcc
1J 2 15 2R D
1K 3 14 2J
1CP 4 13 2K
1S D 5 12 2CP
1Q 6 11 2S D
1Q 7 10 2Q
GND 8 9 2Q
       
Pin Symbol Description
1 1R D asynchronous reset; direct input (active low)
2 1J synchronous input
3 1K synchronous input
4 1CP clock input (low-to-high, edge-triggered)
5 1S D asynchronous set; direct input (active low)
6 1Q true output
7 1Q complement output
8 GND ground
9 2Q complement output
10 2Q true output
11 2S D asynchronous set; direct input (active low)
12 2CP clock input (low-to-high, active low)
13 2K synchronous input
14 2J synchronous input
15 2R D asynchronous reset; direct input (active low)
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, nCP to nQ, nQ 15 (74HC)
17 (74HCT)
ns
Propagation delay, nS D to nQ, nQ 12 (74HC)
14 (74HCT)
ns
Propagation delay, nR D to nQ, nQ 12 (74HC)
15 (74HCT)
ns
Maximum clock frequency 75 (74HC)
61 (74HCT)
MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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