Circuitos Integrados

6821
Peripheral interface adapter
PDF datasheet
       
GND 1  • 40 CA1
PA0 2 39 CA2
PA1 3 38 IRQA
PA2 4 37 IRQB
PA3 5 36 RS0
PA4 6 35 RS1
PA5 7 34 RESET
PA6 8 33 D0
PA7 9 32 D1
PB0 10 31 D2
PB1 11 30 D3
PB2 12 29 D4
PB3 13 28 D5
PB4 14 27 D6
PB5 15 26 D7
PB6 16 25 E
PB7 17 24 CS1
CB1 18 23 CS2
CB2 19 22 CS0
Vcc 20 21 R/W
       
Pin Symbol Description
1 GND ground
2 PA0 port A
3 PA1 port A
4 PA2 port A
5 PA3 port A
6 PA4 port A
7 PA5 port A
8 PA6 port A
9 PA7 port A
10 PB0 port B
11 PB1 port B
12 PB2 port B
13 PB3 port B
14 PB4 port B
15 PB5 port B
16 PB6 port B
17 PB7 port B
18 CB1 peripheral control (port B)
19 CB2 peripheral control (port B)
20 Vcc supply voltage
21 R/W read/write
22 CS0 chip select (active high)
23 CS2 chip select (active low)
24 CS1 chip select (active high)
25 E clock
26 D7 data bus
27 D6 data bus
28 D5 data bus
29 D4 data bus
30 D3 data bus
31 D2 data bus
32 D1 data bus
33 D0 data bus
34 RESET master reset (active low)
35 RS1 register select (address bus)
36 RS0 register select (address bus)
37 IRQB interrupt output (active low)
38 IRQA interrupt output (active low)
39 CA2 peripheral control (port A)
40 CA1 peripheral control (port A)


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Max. clock frequency 1 (6821)
1.5 (68A21)
2 (68B21)
MHz
Pulse width, E low 430 (6821)
280 (68A21)
210 (68B21)
ns
Pulse width, E high 450 (6821)
280 (68A21)
220 (68B21)
ns
Min. RESET pulse length 1 µs

Notes
  • Port A is designed to drive CMOS logic to normal 30%/70% levels.
  • Port B uses three-state NMOS buffers and requires external resistors to pull up to CMOS levels.
  • Port B is capable of driving Darlingtons.
  • When in output mode, a read of Port A returns the actual pin states.
  • When in output mode, a read of Port B returns the contents of the output latch.
  • RS=00, bit 2 of control register A=1: peripheral register A
  • RS=00, bit 2 of control register A=0: data direction register A
  • RS=01: control register A
  • RS=10, bit 2 of control register B=1: peripheral register B
  • RS=10, bit 2 of control register B=0: data direction register B
  • RS=11: control register B

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

BACK