Vss	1  •	40	HALT
NMI	2	39	TSC
IRQ	3	38	LIC
FIRQ	4	37	RESET
BS	5	36	AVMA
BA	6	35	Q
Vcc	7	34	E
A0	8	33	BUSY
A1	9	32	R/W
A2	10	31	D0
A3	11	30	D1
A4	12	29	D2
A5	13	28	D3
A6	14	27	D4
A7	15	26	D5
A8	16	25	D6
A9	17	24	D7
A10	18	23	A15
A11	19	22	A14
A12	20	21	A13

Pin	Symbol	Description
1	Vss	ground
2	NMI	non-maskable interrupt (active low)
3	IRQ	interrupt request (active low)
4	FIRQ	fast interrupt request (active low)
5	BS	bus status output
6	BA	bus available output
7	Vcc	supply voltage
8	A0	address bus
9	A1	address bus
10	A2	address bus
11	A3	address bus
12	A4	address bus
13	A5	address bus
14	A6	address bus
15	A7	address bus
16	A8	address bus
17	A9	address bus
18	A10	address bus
19	A11	address bus
20	A12	address bus
21	A13	address bus
22	A14	address bus
23	A15	address bus
24	D7	data bus
25	D6	data bus
26	D5	data bus
27	D4	data bus
28	D3	data bus
29	D2	data bus
30	D1	data bus
31	D0	data bus
32	R/W	bus read/write
33	BUSY	busy status
34	E	clock input
35	Q	quadrature clock input
36	AVMA	advanced VMA signal (indicates bus will be used in the next cycle)
37	RESET	reset (active low)
38	LIC	last instruction cycle (high during last cycle of instruction)
39	TSC	three-state control (active high; tri-states address, data, R/W )
40	HALT	halt (active low)

Specifications
(typical values under recommended operating conditions, unless specified)

Parameter	Value	Unit
Clock speed	1 (6809E) 1.5 (68A09E) 2 (68B09E)	MHz