Circuitos Integrados

628128
128K x 8 static RAM
PDF datasheet
       
NC 1  • 32 Vcc
A16 2 31 A15
A14 3 30 CS2
A12 4 29 WE
A7 5 28 A13
A6 6 27 A8
A5 7 26 A9
A4 8 25 A11
A3 9 24 OE
A2 10 23 A10
A1 11 22 CS1
A0 12 21 I/O7
I/O0 13 20 I/O6
I/O1 14 19 I/O5
I/O2 15 18 I/O4
GND 16 17 I/O3
       
Pin Symbol Description
1 NC no connection
2 A16 address input
3 A14 address input
4 A12 address input
5 A7 address input
6 A6 address input
7 A5 address input
8 A4 address input
9 A3 address input
10 A2 address input
11 A1 address input
12 A0 address input
13 I/O0 data input/output
14 I/O1 data input/output
15 I/O2 data input/output
16 GND ground
17 I/O3 data input/output
18 I/O4 data input/output
19 I/O5 data input/output
20 I/O6 data input/output
21 I/O7 data input/output
22 CS1 chip select (active low)
23 A10 address input
24 OE output enable (active low)
25 A11 address input
26 A9 address input
27 A8 address input
28 A13 address input
29 WE write enable (active low)
30 CS2 chip select (active high)
31 A15 address input
32 Vcc supply voltage

Notes
  • Data is written when CS1 is low, CS2 is high, and WE is low.
  • Data is read when CS1 is low, CS2 is high, OE is low, and WE is high.
  • The input/output pins assume a high-impedance state if CS1 is high or CS2 is low.

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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