Circuitos Integrados

4557
1-to-64 bit variable length shift register
PDF datasheet
       
L2 1  • 16 Vcc
L1 2 15 L4
MR 3 14 L8
CP0 4 13 L16
CP 1 5 12 L32
DB 6 11 Q
DA 7 10 Q
GND 8 9 A/B
       
Pin Symbol Description
1 L2 length control input
2 L1 length control input
3 MR asynchronous master reset
4 CP0 clock input (low-to-high edge-triggered)
5 CP 1 clock input (high-to-low edge-triggered)
6 DB data input
7 DA data input
8 GND ground
9 A/B select data input
10 Q output
11 Q complementary output
12 L32 length input
13 L16 length input
14 L8 length input
15 L4 length input
16 Vcc supply voltage

Notes
  • The length of the shift register is determined by the sum of the length inputs (L1 , L2 , L4 , L8 , L16 , L32 ) plus one.
  • Data is shifted in on the low-to-high transition of CP0 when CP 1 is low, or the high-to-low transition of CP 1 when CP0 is high.
  • When A/B is high, a clock pulse shifts in data from DA . When low, a clock pulse shifts in data from DB .
  • When MR is high, the register is reset, Q is forced low, and Q is forced high.

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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