Integrated Circuits

Z80PIO
Z80-PIO
PDF datasheet
       
D2 1  • 40 D5
D7 2 39 D4
D6 3 38 D3
CE 4 37 M1
C/D 5 36 IORQ
B/A 6 35 RD
PA7 7 34 PB7
PA6 8 33 PB6
PA5 9 32 PB5
PA4 10 31 PB4
GND 11 30 PB3
PA3 12 29 PB2
PA2 13 28 PB1
PA1 14 27 PB0
PA0 15 26 +5V
ASTB 16 25 CLK
BSTB 17 24 IEI
ARDY 18 23 INT
D0 19 22 IEO
D1 20 21 BRDY
       
Pin Symbol Description
1 D2 Data Line 2 To CPU (Bi-Directional)
2 D7 Data Line 7 To CPU (Bi-Directional)
3 D6 Data Line 6 To CPU (Bi-Directional)
4 CE Chip Enable Input (Active Low)
5 C/D Control/Data Select (High = Ctrl, Low = Data)
6 B/A Port A or B Select (Low = A, High = B)
7 PA7 Peripheral Port A Line 7 (Bi-Directional)
8 PA6 Peripheral Port A Line 6 (Bi-Directional)
9 PA5 Peripheral Port A Line 5 (Bi-Directional)
10 PA4 Peripheral Port A Line 4 (Bi-Directional)
11 GND Power Ground
12 PA3 Peripheral Port A Line 3 (Bi-Directional)
13 PA2 Peripheral Port A Line 2 (Bi-Directional)
14 PA1 Peripheral Port A Line 1 (Bi-Directional)
15 PA0 Peripheral Port A Line 0 (Bi-Directional)
16 ASTB Port A Strobe Input from Peripheral (Active Low)
17 BSTB Port B Strobe Input from Peripherial (Active Low)
18 ARDY Register A Ready Output (Active High)
19 D0 Data Line 0 To CPU (Bi-Directional)
20 D1 Data Line 1 To CPU (Bi-Directional)
21 BRDY Register B Ready Output (Active High)
22 IEO Interrupt Enable Output (Active High)
23 INT Interrupt Input (Active Low)
24 IEI Interrupt Enable Input (Active High)
25 CLK System Clock Input
26 +5V Power 5V DC
27 PB0 Peripheral Port A Line 0 (Bi-Directional)
28 PB1 Peripheral Port A Line 1 (Bi-Directional)
29 PB2 Peripheral Port A Line 2 (Bi-Directional)
30 PB3 Peripheral Port A Line 3 (Bi-Directional)
31 PB4 Peripheral Port A Line 4 (Bi-Directional)
32 PB5 Peripheral Port A Line 5 (Bi-Directional)
33 PB6 Peripheral Port A Line 6 (Bi-Directional)
34 PB7 Peripheral Port A Line 7 (Bi-Directional)
35 RD Read Request Input from CPU (Active Low)
36 IORQ Input/Output Request Input from CPU (Active Low)
37 M1 Machine Cycle 1 Input from CPU (Active Low)
38 D3 Data Line 3 To CPU (Bi-Directional)
39 D4 Data Line 4 To CPU (Bi-Directional)
40 D5 Data Line 5 To CPU (Bi-Directional)


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Maximum Voltage Vcc 7.0 VDC
Maximum Input Voltage Vcc + 0.3 VDC
Storage Temperature -65 to +150 Degrees C

Notes
  • The Z8O Parallel I/O (PlO) Circuit is a programmable, two port device which provides a TTL compatible interface between peripheral devices and the Z80-GPU. The CPU can configure the Z8O-PIO to interface with a wide range of peripheral devices with no other external logic required, Typical peripheral devices that are fully compatible with the Z80-PIO include most keyboards, paper tape readers and punches, printers, PROM programmers, etc. The Z8O-PIO is packaged in a 40-pin DIP, or a 44-pin PLCC, or a 44-pin OFP. NMOS and CMOS versions are also available. Major features of the Z80-PlO include.
  • One of the unique features of the Z80-PlO that separates it from other interface controllers is that all data transfer between the peripheral device and the CPU is accomplished under total interrupt control. The interrupt logic of the PIO permits full usage of the efficient interrupt capabilities of the Z80-CPU during I/0 transfers. All logic necessary to implement a fully nested interrupt structure is included in the PIO so that additional circuits are not required. Another unique feature of the PlO is that it can be programmed to interrupt the CPU on the occurrence of specified status conditions in the peripheral device. For example, the PlO can be programmed to interrupt if any specified peripheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor must spend in polling peripheral status.

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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