Integrated Circuits

7473
Dual J-K flip-flop with reset; negative-edge trigger
PDF datasheet
       
1CP 1  • 14 1J
1R 2 13 1Q
1K 3 12 1Q
Vcc 4 11 GND
2CP 5 10 2K
2R 6 9 2Q
2J 7 8 2Q
       
Pin Symbol Description
1 1CP clock input (high-to-low edge-triggered)
2 1R asynchronous reset (active low)
3 1K synchronous K input
4 Vcc supply voltage
5 2CP clock input (high-to-low edge-triggered)
6 2R asynchronous reset (active low)
7 2J synchronous J input
8 2Q complement output
9 2Q true output
10 2K synchronous K input
11 GND ground
12 1Q true output
13 1Q complement output
14 1J synchronous J input


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, nCP to nQ 16 (74HC) ns
Propagation delay, nCP to nQ 16 (74HC) ns
Propagation delay, nR to nQ, nQ 15 (74HC) ns
Maximum frequency 77 (74HC) MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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