Integrated Circuits

74194
4-bit bidirectional universal shift register
PDF datasheet
       
MR 1  • 16 Vcc
DSR 2 15 Q0
D0 3 14 Q1
D1 4 13 Q2
D2 5 12 Q3
D3 6 11 CP
DSL 7 10 S1
GND 8 9 S0
       
Pin Symbol Description
1 MR asynchronous master reset (active low)
2 DSR serial data input (shift right)
3 D0 parallel data input
4 D1 parallel data input
5 D2 parallel data input
6 D3 parallel data input
7 DSL serial data input (shift left)
8 GND ground
9 S0 mode control input
10 S1 mode control input
11 CP clock input (low-to-high, edge-triggered)
12 Q3 parallel output
13 Q2 parallel output
14 Q1 parallel output
15 Q0 parallel output
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, CP to Qn 14 (74HC)
15 (74HCT) 		ns
Propagation delay, MR to Qn 14 (74HC)
15 (74HCT) 		ns
Maximum clock frequency 102 (74HC)
77 (74HCT) 		MHz

Notes
  • S0 and S1 are low; hold (do nothing)
  • S0 low and S1 high; shift left
  • S0 high and S1 low; shift right
  • S0 and S1 high; parallel load

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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