Integrated Circuits

74175
Quad D-type flip-flop with reset; positive-edge trigger
PDF datasheet
       
MR 1  • 16 Vcc
Q0 2 15 Q3
Q 0 3 14 Q 3
D0 4 13 D3
D1 5 12 D2
Q 1 6 11 Q 2
Q1 7 10 Q2
GND 8 9 CP
       
Pin Symbol Description
1 MR asynchronous master reset (active low)
2 Q0 flip-flop output
3 Q 0 complementary flip-flop output
4 D0 data input
5 D1 data input
6 Q 1 complementary flip-flop output
7 Q1 flip-flop output
8 GND ground
9 CP clock input (low-to-high, edge-triggered)
10 Q2 flip-flop output
11 Q 2 complementary flip-flop output
12 D2 data input
13 D3 data input
14 Q 3 complementary flip-flop output
15 Q3 flip-flop output
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, CP to Qn , Q n 17 (74HC)
16 (74HCT) 		ns
Propagation delay, MR to Qn 15 (74HC)
19 (74HCT) 		ns
Maximum clock frequency 83 (74HC)
54 (74HCT) 		MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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