Integrated Circuits

74174
Hex D-type flip-flop with reset; positive-edge trigger
PDF datasheet
       
MR 1  • 16 Vcc
Q0 2 15 Q5
D0 3 14 D5
D1 4 13 D4
Q1 5 12 Q4
D2 6 11 D3
Q2 7 10 Q3
GND 8 9 CP
       
Pin Symbol Description
1 MR asynchronous master reset (active low)
2 Q0 flip-flop output
3 D0 data input
4 D1 data input
5 Q1 flip-flop output
6 D2 data input
7 Q2 flip-flop output
8 GND ground
9 CP clock input (low-to-high, edge-triggered)
10 Q3 flip-flop output
11 D3 data input
12 Q4 flip-flop output
13 D4 data input
14 D5 data input
15 Q5 flip-flop output
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, CP to Qn 17 (74HC)
18 (74HCT) 		ns
Propagation delay, MR to Qn 13 (74HC)
17 (74HCT) 		ns
Maximum clock frequency 99 (74HC)
69 (74HCT) 		MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

BACK