Integrated Circuits

74173
Quad D-type flip-flop; positive-edge trigger; 3-state
PDF datasheet
       
OE 1 1  • 16 Vcc
OE 2 2 15 MR
Q0 3 14 D0
Q1 4 13 D1
Q2 5 12 D2
Q3 6 11 D3
CP 7 10 E 2
GND 8 9 E 1
       
Pin Symbol Description
1 OE 1 output enable input (active low)
2 OE 2 output enable input (active low)
3 Q0 3-state flip-flop output
4 Q1 3-state flip-flop output
5 Q2 3-state flip-flop output
6 Q3 3-state flip-flop output
7 CP clock input (low-to-high, edge-triggered)
8 GND ground
9 E 1 data enable input (active low)
10 E 2 data enable input (active low)
11 D3 data input
12 D2 data input
13 D1 data input
14 D0 data input
15 MR asynchronous master reset (active high)
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, CP to Qn 17 (74HC/HCT) ns
Propagation delay, MR to Qn 13 (74HC)
17 (74HCT) 		ns
Maximum clock frequency 88 (74HC/HCT) MHz

Notes
  • When one or both OE n inputs are high, the outputs are forced to a high-impedance off state.

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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