Integrated Circuits

74112
Dual J-K flip-flop with set and reset; negative-edge trigger
PDF datasheet
       
1CP 1  • 16 Vcc
1K 2 15 1R D
1J 3 14 2R D
1S D 4 13 2CP
1Q 5 12 2K
1Q 6 11 2J
2Q 7 10 2S D
GND 8 9 2Q
       
Pin Symbol Description
1 1CP clock input (high-to-low, edge-triggered)
2 1K synchronous input
3 1J synchronous input
4 1S D asynchronous set; direct input (active low)
5 1Q true output
6 1Q complement output
7 2Q complement output
8 GND ground
9 2Q true output
10 2S D asynchronous set; direct input (active low)
11 2J synchronous input
12 2K synchronous input
13 2CP clock input (high-to-low, edge-triggered)
14 2R D asynchronous reset; direct input (active low)
15 1R D asynchronous reset; direct input (active low)
16 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, nCP to nQ, nQ 17 (74HC)
19 (74HCT) 		ns
Propagation delay, nS D to nQ, nQ 15 (74HC)
15 (74HCT) 		ns
Propagation delay, nR D to nQ, nQ 18 (74HC)
19 (74HCT) 		ns
Maximum clock frequency 66 (74HC)
70 (74HCT) 		MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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