Integrated Circuits

74107
Dual J-K flip-flop with reset; negative-edge trigger
PDF datasheet
       
1J 1  • 14 Vcc
1Q 2 13 1R
1Q 3 12 1CP
1K 4 11 2K
2Q 5 10 2R
2Q 6 9 2CP
GND 7 8 2J
       
Pin Symbol Description
1 1J synchronous input
2 1Q complement output
3 1Q true output
4 1K synchronous input
5 2Q true output
6 2Q complement output
7 GND ground
8 2J synchronous input
9 2CP clock input (high-to-low, edge-triggered)
10 2R asynchronous reset (active low)
11 2K synchronous input
12 1CP clock input (high-to-low, edge-triggered)
13 1R asynchronous reset (active low)
14 Vcc supply voltage


Specifications
(typical values under recommended operating conditions, unless specified)
Parameter Value Unit
Propagation delay, nCP to nQ 16 (74HC)
16 (74HCT)
ns
Propagation delay, nCP to nQ 16 (74HC)
18 (74HCT)
ns
Propagation delay, nR to nQ, nQ 16 (74HC)
17 (74HCT)
ns
Maximum clock frequency 78 (74HC)
73 (74HCT)
MHz

Note
Data is maintained by an independent source and accuracy is not guaranteed. Check with the manufacturer's datasheet for up-to-date information.

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